Many semiconductor memory devices contain one or more redundant rows or columns of memory cells. During initial testing of each memory chip the test routine looks for device failures. If the number of rows or columns in the memory chip containing device failures is less than or equal to the number of redundant rows or columns, then the redundant rows or columns are "programmed" so as to replace the columns containing defective cells.
FIG. 1 shows a block diagram of a memory device with a redundant memory circuit. An array 100 of memory cells is shown here as a set of columns 102, including at least one defective column 104. In other words, there is a column 104 of memory cells which contains at least one defective element, which may be a defective cell, a broken or high resistance bit line, a defective sense amplifier, etc. Also shown is a simplified diagram of the column decoder circuitry 106 which selects a column 102 in accordance with address signals AO through An.
A redundancy usage control circuit 108 includes a number of programmable circuit elements 110. The redundancy usage control circuit 108 produces a high signal on its output line 112 when selecting redundant column 114. The programmable circuit elements 110 would be programmed in such a manner that when defective column 104 is selected by the address signals, the output 112 of the redundancy control circuit 108 will be high. Consequently, redundant column 114 will be selected. When the output of the redundancy control circuit 108 is high, the output of invertor 116 will be low. The output of this invertor 116 is connected to the input of all the AND gates 118 that are used to decode the column address signals. Thus the output of each AND gate 118 in decoder 106 will be low when the redundancy control circuit 108 selects the redundant column 114. Hence, when defective column 104 is addressed, the decoder 106 is disabled to prevent access to defective column 104, and the redundant column 114 is selected instead.
One method of performing the programming of the cells 110 in the redundancy control circuit 108 is to employ fusible silicon links (see, for example, U.S. Pat. No. 3,792,319). Another technique used to program redundant rows or columns is called laser programming, in which a set of metal line connections can be selectively removed by a laser so as to program the redundancy circuit. Both of these techniques have problems which make them undesirable, although laser programming is widely used.
The present invention specifically concerns redundancy circuits for EPROM memory devices, and particularly the use of non-erasable EPROM cells as the programmable circuit elements 110 in the redundancy control circuit 108 of FIG. 1. The seminal patents in this area of semiconductor memory technology are U.S. Pat. Nos. 4,358,833, 4,441,170, 4,519,050 and 4,530,074, all of which are assigned to Intel Corporation of Santa Clara, California. U.S. Pat. Nos. 4,358,833, 4,441,170, 4,519,050 and 4,530,074 (herein called the Intel patents) are hereby incorporated by reference.
The basic idea behind the non-erasable EPROM cells in the aforementioned prior art patents is shielding a set of otherwise standard EPROM cells to form the programmable circuit elements 110 of a redundancy control circuit 108, thereby preventing the shielded cells from being erased when the memory device is exposed to ultraviolet radiation for a prolonged period of time so as to erase the data stored in all the regular EPROM memory cells in the array 100. In this way, the shielded EPROM memory cells 110 in the redundancy control circuit 108 can be fabricated on the same substrate as electrically programmable EPROM cells which are erased when exposed to ultraviolet radiation.
The shielded EPROM cells used in the Intel patents are vulnerable to light which scatters and reflects under the shielding. Therefore the shielding in the Intel patents is designed to make the path for propagating light under the shielding very long so as to cause most of this reflected light to be absorbed and otherwise dissipated before reaching the shielded cells. More particularly, a set of long serpentine drain connections are used to reduce the effect of light reflected under the shield on the shielded EPROM cells. As a result, Intel's shielded EPROM cells consume a very large amount of semiconductor surface area. A typical set of four shielded memory cells will occupy approximately 10,000 square microns using 1.0 micron design rules.
The object of the present invention is to provide shielded EPROM memory cells for use in a redundancy control circuit which occupy significantly less area than those disclosed in the Intel patents, thereby making the use of such shielded cells less expensive and more commercially viable. Another object of the present invention is to provide a shield for EPROM cells which effectively blocks radiation from reaching the shielded cells without using a set of serpentine drain connections.